VLSI Practice Test 7

1. ______ of the runs will have a length of 1.

2. Which occupies a lesser area?

3. Test generation effort for n gate circuit is proportional to

4. To avoid self resetting, the tester can be over ridden by adding

5. The LFSR takes reasonable time if the n value is

6. In this iterative test generation method, sequential logic is

7. To access directly another system ______ is done.

8. Storage elements in scan design technique is reconfigured to form

9. Boundary scan method takes lesser time on test pattern generation.

10. In which mode, storage elements are used independently?