VLSI Mock Test 3 - Sanfoundry

10%

Question 1 of 10

1. For semiconductors doped through diffusion or through surface peaked ion implantation we derive the sheet resistance as ___________

Average resistivity of semiconductor/thickness

Resistivity/thickness

Conductivity/thickness

None of the mentioned

Question 1 of 10

Question 2 of 10

2. What is the value of gate capacitance?

0.25 square Cg

1.5 square Cg

1 square Cg

1.25 square Cg

Question 2 of 10

Question 3 of 10

3. The junction parasitic capacitance are produced due to ____________

Source diffusion regions

All of the mentioned

Gate diffusion regions

Drain diffusion region

Question 3 of 10

Question 4 of 10

4. Diffusion capacitance is equal to ___________

area capacitance

peripheral capacitance

fringing field capacitance

area capacitance + peripheral capacitance

Question 4 of 10

Question 5 of 10

5. Peripheral capacitance is given in _________ eper unit length.

nano farad

farad

micro farad

pico farad

Question 5 of 10

Question 6 of 10

6. In saturation mode operation, gate to drain capacitance is zero due to ___________

Drain is connected to ground

Inversion layer doesn’t exist

Gate and drain are interconnected

Channel length is reduced

Question 6 of 10

Question 7 of 10

7. What is the transition point of an inverter?

0.5 Vdd

Vdd

0.25 Vdd

2 Vdd

Question 7 of 10

Question 8 of 10

8. When MOSFET is operating in saturation region, the gate to source capacitance is?

Cox*W*L

2/3*Cox*W*L

1/2*Cox*W*L

1/3*Cox*W*L

Question 8 of 10

Question 9 of 10

9. The voltage gain of the MOSFET is given by:

None of the mentioned

Av = -βRd

Av = γRd

Av = -gmRd

Question 9 of 10

Question 10 of 10

10. During the calculation of load capacitance of a 1st stage CMOS inverter, the input node capacitances, Cgs, n and Cgs, p of the 2nd stage CMOS inverter is also considered.

False

True

Question 10 of 10