VLSI Mock Test 5 - Sanfoundry

10%

Question 1 of 10

1. Which must be given the highest priority in design process?

communication

colour

architecture

thickness

Question 1 of 10

Question 2 of 10

2. In inverter during logic 1 to 0 transition, capacitance discharges at

pull-down resistance

both pull-up and pull-down

pull-up resistance

at gate

Question 2 of 10

Question 3 of 10

3. Static RAM uses ____________ transistors.

six

seven

four

five

Question 3 of 10

Question 4 of 10

4. If the input of type 1 PLL is a frequency step of Δw at t = 0, the change in phase at t = infinity is:

Δw

None of the mentioned

Δw/Kpd

Δw/Kpd.Kvco

Question 4 of 10

Question 5 of 10

5. Which is not suitable for circuits having large N values?

deterministic test pattern method

pseudo-exhaustive test pattern method

random test pattern method

exhaustive test pattern method

Question 5 of 10

Question 6 of 10

6. The shifter must be connected to

2-shift control line

2-shift data line

4-shift control line

4-shift data line

Question 6 of 10

Question 7 of 10

7. In which method sequences are repeatable?

pseudo-exhaustive test pattern method

random test pattern method

exhaustive test pattern method

pseudo-random test pattern method

Question 7 of 10

Question 8 of 10

8. If the current density exceeds a threshold value then metal atoms moves in

doesnt depend on direction of current

direction of the current

direction of the voltage

opposite direction of the current

Question 8 of 10

Question 9 of 10

9. The area of CMOS inverter is proportional to

area of n device

area of p device

square of minimum feature size

total area of n and p device

Question 9 of 10

Question 10 of 10

10. To minimize the design effort, regularity should be

low

high

very low

very high

Question 10 of 10