VLSI Practice Test 10

1. Design rule is not influenced by maturity of property line.

2. The current through the n-MOS transistor will flow when:

3. Field effect transistor's conductivity is regulated by

4. If VIH of the 2nd gate is lower than VOH of the 1st gate, then logic output 0 from the 1st gate is considered as:

5. The ratio of Zp.u./Zp.d. for E-MESFET is

6. Flicker noise is found in MOSFET at:

7. Which color is used to represent first level metal?

8. The MESFET properties can be varied by varying the

9. For equal margin, Vinv is set as ______ of logic voltage swing.

10. When gate voltage is negative for enhancement mode n-MOS, the direction of electric field will be: