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VLSI Online Test


Correct Answer: 2 points | Wrong: -1 point
Grades: A* (100% score) | A (80%-99%) | B (60%-80%) | C (40%-60%) | D (0%-40%)
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Here is the complete list of test quizzes on VLSI.

1. Inverter threshold voltage is the point where

Question 1 of 50

2. Which region is heavily doped?

Question 2 of 50

3. VLSI design is done in _________ approach.

Question 3 of 50

4. P-well is created on __________

Question 4 of 50

5. Rifts and extensions should be placed in

Question 5 of 50

6. In Constant voltage model the gate capacitance is scaled by a factor of:

Question 6 of 50

7. In resistive region __________

Question 7 of 50

8. Boundary scan method takes lesser time on test pattern generation.

Question 8 of 50

9. Switch logic is designed using

Question 9 of 50

10. In nMOS device, gate material could be ____________

Question 10 of 50

11. The scaling factor of Gate delay in Constant field model is:

Question 11 of 50

12. In the ring diagram, green line is used to represent

Question 12 of 50

13. Practical guidelines for testability aims at

Question 13 of 50

14. Which color is used for polysilicon?

Question 14 of 50

15. In Cut-off Mode, the capacitance Cgs will be equal to ___________

Question 15 of 50

16. In GaAs __________ has more intrinsic mobility.

Question 16 of 50

17. The current Ids _______ as Vds increases.

Question 17 of 50

18. Transient faults does not depend on operating condition.

Question 18 of 50

19. Which method is used for external functional testing?

Question 19 of 50

20. Rise time and fall time can be also equalized by

Question 20 of 50

21. __________ is needed to facilitate turn-off.

Question 21 of 50

22. A metallic blob present between drain and the ground of the n-MOSFET inverter acts as:

Question 22 of 50

23. What is the desired or safe delay value for 5 micron technology?

Question 23 of 50

24. The 2 types of noise that the analog systems face during signal processing are:

Question 24 of 50

25. For the formation of E-MESFET _______ is used.

Question 25 of 50

26. When a clock signal is gated with another signal like load signal, output is not affected.

Question 26 of 50

27. The poor controllability circuits are:

Question 27 of 50

28. In CMOS logic circuit the n-MOS transistor acts as:

Question 28 of 50

29. The total delay for the select register circuit is

Question 29 of 50

30. For 5 micron technology, What is the Rs value for a metal?

Question 30 of 50

31. Which method is used to determine structural defects?

Question 31 of 50

32. In consistency/ justification, tracking is done

Question 32 of 50

33. IDDQ fault occurs when there is

Question 33 of 50

34. BJT gain should be ______ to avoid latch-up effect.

Question 34 of 50

35. Propagation time is directly proportional to ____________

Question 35 of 50

36. In gallium arsenide, radiation resistance is

Question 36 of 50

37. Computer-assisted graphical entry is done through

Question 37 of 50

38. The scaling factor of current density in constant voltage model is:

Question 38 of 50

39. For constant voltage model,

Question 39 of 50

40. Hot carrier injection causes

Question 40 of 50

41. _______ is used to start the initial sequence correctly.

Question 41 of 50

42. The high current driving capability of the BiCMOS is due to __________

Question 42 of 50

43. Current flows only when

Question 43 of 50

44. In the below circuit if the current source is ideal, the voltage gain is:
Find the voltage gain if the current source is ideal

Question 44 of 50

45. The output conductance value in cut off region is

Question 45 of 50

46. The conduction of current IDS depends on:

i) Gate to source voltage
ii) Drain to source voltage
iii) Bulk to source voltage
iv) Threshold voltage
v) Dimensions of MOSFET

Question 46 of 50

47. What can be introduced to reduce the latch-up effect?

Question 47 of 50

48. According to body effect, substrate is biased with respect to ___________

Question 48 of 50

49. Large AND function will produce _______ infrequently.

Question 49 of 50

50. For semiconductors doped through diffusion or through surface peaked ion implantation we derive the sheet resistance as ___________

Question 50 of 50


 

Topic wise Test Quizzes on VLSI

VLSI tests, quizzes, and exams are great ways to learn and test your VLSI skills. Whether you’re a beginner or experienced, challenge and boost your confidence with our engaging online quizzes on VLSI Basics, MOS Fabrication, Circuit Parameter and Delay, Capacitance, Amplifier, MOS Circuits Scaling, Digital Logic and CMOS, VLSI Design Process, Testability and Scan Techniques, VLSI CMOS, GaAs, VLSI Fabrication and MOS Transistor Theory. Start the VLSI online test now!

VLSI Certification Test

VLSI Certification Test is a free certification exam. However, you need to score at least a B grade in the “Qualifier Test” to be eligible to take part in this test. So, take the “Qualifier Test” before the Certification test.

Total Questions: 50, Total Time: 1 hour, Correct Answer: 2 points, Wrong Answer: -1 point

VLSI Internship Test

If you scored either Grade A* or Grade A in our VLSI Internship Test, then you can apply for Internship at Sanfoundry in VLSI.

Total Questions: 50, Total Time: 1 hour, Correct Answer: 2 points, Wrong Answer: -1 point

VLSI Job Test

It’s designed to test and improve your skills for a successful career, as well as to apply for jobs.

Total Questions: 50, Total Time: 1 hour, Correct Answer: 2 points, Wrong Answer: -1 point

  
Note: Before you get started on these series of online tests, you should practice our collection of 1000 MCQs on VLSI here.

Sanfoundry Scoring & Grading System

Sanfoundry tests and quizzes are designed to provide a real-time online exam experience. Here’s what you need to know about them.

  • Scoring System: You get 2 points for each correct answer but lose 1 point for every wrong answer.
  • Grading System: Your grade depends on your final score and can be one of the following:
    • Grade A* – Genius (100%)
    • Grade A – Excellent (80% to 99%)
    • Grade B – Good (60% to 80%)
    • Grade C – Average (40% to 60%)
    • Grade D – Poor (0% to 40%)
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Manish Bhojasia - Founder & CTO at Sanfoundry
Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He lives in Bangalore, and focuses on development of Linux Kernel, SAN Technologies, Advanced C, Data Structures & Alogrithms. Stay connected with him at LinkedIn.

Subscribe to his free Masterclasses at Youtube & discussions at Telegram SanfoundryClasses.