VLSI Practice Test 5

1. Which design is preferred in n-bit adder?

2. FOR nMOS which implementation is not suitable?

3. The truth table which accurately explains the operation of CMOS not gate is:

4. The shifter must be connected to

5. The block diagram of basic PLL consists of:

6. What is the delay required to perform a single operation in a pipelined structure?

7. Rise time and fall time can be equalized by

8. Number of poles in Type 1 PLL is:

9. Good design system has regularity in the range of

10. Equalizing of rise time and fall time is possible in