VLSI Practice Test 3

1. The junction parasitic capacitance are produced due to ____________

2. The sheet resistance of the conducting material is?

3. In MOSFET amplifier, the input is applied as:

4. The amount of parasitic capacitance at the output node is determined by __________

5. Interconnect capacitance contributes to the load capacitance when the CMOS inverters are connected in cascade configuration.

6. In the below circuit if the current source is ideal, the voltage gain is:

7. The Differential output of the difference amplifier is the amplification of __________

8. Peripheral capacitance is given in _________ eper unit length.

9. The total resistance can be given as ___________

10. Interlayer capacitance occurs due to ___________