VHDL Practice Test 8

1. What is the process of flattening?

2. How does keyword inertial affect an assignment statement?

3. Generate statements can’t be nested.

4. If we don’t use any keyword in the function definition, then which of the following is the type of function?

5. ACCESS type can’t be used in ________ directly.

6. The word LABEL is not reserved in VHDL.

7. As a VHDL designer, what should you make sure about the design so that it is synthesized correctly?

8. What is realized in the code given below?

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY my_logic IS
GENERIC n : INTEGER := 8;
PORT (sig1 : bit_vector(n-1 DOWNTO 0);
             Sig2 : bit_vector(n-1 DOWNTO 0));
END my_logic;
ARCHITECTURE test OF my_logic IS
COMPONENT or2
   PORT(a0, a1 : IN BIT;
                z         : OUT BIT);
END COMPONENT or
BEGIN
ORARRAY : FOR i IN (n-1) DOWNTO 0 GENERATE
                   or_gate : or2
PORT MAP ( a0 => sig1(i),
                       A1 => sig2(i),
                         z => y(i));
END GENERATE ORARRAY;
END test;

9. NULL keyword is most of the time useful with _______ part of _______ statement.

10. There are _______ types of GENERATE statement in VHDL.