VHDL Mock Test 1 - Sanfoundry

10%

Question 1 of 10

1. An UNSIGNED type is always greater than zero.

False

True

Question 1 of 10

Question 2 of 10

2. Which of the following is used at the end of a statement?

_ (underscore)

No sign is used at the end of statement

; (Semicolon)

-- ( double hyphen)

Question 2 of 10

Question 3 of 10

3. How to control the structure and timing of the entity can be changed?

By using TIME variable in the entity

By using some special code

By changing the entity declaration from time to time

By using GENERICS

Question 3 of 10

Question 4 of 10

4. What is the meaning of the base unit?

CGS unit for any physical literal

Fundamental building block of any design

Smallest possible unit of any physical literal

SI unit of any physical literal

Question 4 of 10

Question 5 of 10

5. Which of the following is not a back end EDA tool?

Routing tools

Floor planning tools

Placement tools

Simulators

Question 5 of 10

Question 6 of 10

6. A package in VHDL consists of _________

Commonly used tools

Commonly used architectures

Commonly used data types and subroutines

Commonly used syntax and variables

Question 6 of 10

Question 7 of 10

7. Complete description of the circuit to be designed is given in _________

Library

Configurations

Architecture

Entity

Question 7 of 10

Question 8 of 10

8. Which of the following can be the name of an architecture?

architecture

1arch

arch 1

arch_1

Question 8 of 10

Question 9 of 10

9. What is the difference between SIGNAL and VARIABLE?

SIGNAL depends upon VARIABLE for various operations

The value of SIGNAL never varies whereas VARIABLE can change its value

SIGNAL is global and VARIABLE is local to the process in which it is declared

SIGNAL can be used for input or output whereas VARIABLE acts as intermediate signals

Question 9 of 10

Question 10 of 10

10. On which side of assignment operator, we can use the IN type signal?

Left

Can’t be used

Right

Both

Question 10 of 10