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VHDL Online Test


Correct Answer: 2 points | Wrong: -1 point
Grades: A* (100% score) | A (80%-99%) | B (60%-80%) | C (40%-60%) | D (0%-40%)

Here is the complete list of test quizzes on VHDL.

1. Which of the following is the right way to leave a port unconnected?

Question 1 of 50

2. The function conv_std_logic_vector(p,b) is used for_______

Question 2 of 50

3. What is the correct syntax for using ASSERT statement?

Question 3 of 50

4. Process is a _______ statement.

Question 4 of 50

5. It is necessary to use configuration to bind entity to the architecture in case of structural modeling.

Question 5 of 50

6. What is the difference between OUT and BUFFER?

Question 6 of 50

7. Which of the following is not a reserved word in VHDL?

Question 7 of 50

8. a < = b after 10ns; In this statement the keyword ‘after’ is used for introducing delay.

Question 8 of 50

9. What logic is described in the following logic?

PROCESS (a, b)
IF (a = ‘1’ AND b = ‘0’ OR a= ’0’ AND b = ‘1’) THEN
y <= ‘1’;
ELSIF (a = ‘1’ AND b= ‘1’) THEN
y <= ‘0’;
ELSE
 y <= ‘0’;
END IF

Question 9 of 50

10. What kind of statement is the IF statement?

Question 10 of 50

11. Where should one use WARNING severity level?

Question 11 of 50

12. Which of the following is a variable assignment statement?

Question 12 of 50

13. A buffer with single input A and single output B has a delay of 20 nanosecond. If the value of input A changes after 10 ns from 0 to 1 and it changes again from 1 to 0 at 20 ns. At what time, the value of output B will be 1, if the inertial delay model is used?

Question 13 of 50

14. In the combinational process, the use of output signal in the sensitivity list is illegal.

Question 14 of 50

15. It is possible to define a new operator ++ in VHDL.

Question 15 of 50

16. Which of the following statements can be seen as sequential equivalent to the selected concurrent assignment?

Question 16 of 50

17. What is the basic unit of structural modeling?

Question 17 of 50

18. Which of the following statement is correct to check the violation of hold time?

Question 18 of 50

19. Loop is a ________ statement.

Question 19 of 50

20. In __________ counter universal clock is not used.

Question 20 of 50

21. More than one generic parameter can be defined in a single entity.

Question 21 of 50

22. Mealy type FSM has a memory element.

Question 22 of 50

23. A function is a ________ code.

Question 23 of 50

24. The use of ERROR severity is _________

Question 24 of 50

25. The keyword TRANSPORT in any assignment statement specifies _______

Question 25 of 50

26. In which of the following library, the package STANDARD defined?

Question 26 of 50

27. Which of the following keyword is used to identify a clocked process?

Question 27 of 50

28. RECORD in VHDL is similar to________ in C.

Question 28 of 50

29. User can define its own integer data type.

Question 29 of 50

30. Which of the following keyword was not present before VHDL 93?

Question 30 of 50

31. The variables declared inside a function retain their values between two function calls.

Question 31 of 50

32. Which of the following describes the structure of VHDL code correctly?

Question 32 of 50

33. The maximum number of parameters in port map() function while implementing logic function using gates only, is equal to ____________

Question 33 of 50

34. Value attributes are classified into _______ subclasses.

Question 34 of 50

35. What will be the values of out1 and out2?

ARCHITECTURE bhv OF example IS
CONSTANT out1 : BIT;
CONSTANT out2 : BIT;
BEGIN
B1 : BLOCK
CONSTANT S : BIT := 0;
BEGIN
B1-1 : BLOCK
SIGNAL S : BIT := 1;
BEGIN
out1 <= S;
END BLCOK B1-1;
out2 <= S;
END BLOCK B1;
END bhv;

Question 35 of 50

36. The top-level system design is modelled for functionality and performance.

Question 36 of 50

37. What is the minimum number of NAND gates required to implement an EXOR gate?

Question 37 of 50

38. Which of the following method is not used to remove the race around condition in a flip flop?

Question 38 of 50

39. Which of the following could be the objects in the parameter list of a procedure?

Question 39 of 50

40. What are the two constructs used in most of the behavioural modelling?

Question 40 of 50

41. In an assignment statement, OUT signal can be used only to the ___________

Question 41 of 50

42. Which data object can’t be declared inside a process?

Question 42 of 50

43. Which of the following is not representing a nibble?

Question 43 of 50

44. Which of the following returns TRUE if there is no component instantiation statement in the block?

Question 44 of 50

45. In synchronous reset, reset is sampled with respect to _______

Question 45 of 50

46. Any item declared in a package declaration section are visible to _______

Question 46 of 50

47. Which of the following is similar to the entity declaration in structural modeling?

Question 47 of 50

48. Which of the following is not a part of the configuration statement?

Question 48 of 50

49. If a and b are two STD_LOGIC_VECTOR input signals, then legal assignment for a and b is?

Question 49 of 50

50. Which logic circuit is described in the following code?

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY system IS
GENERIC (l : INTEGER := 3);
PORT ( a, b : IN STD_LOGIC_VECTOR ( l DOWNTO 0);
              c     : IN STD_LOGIC;
              x     : OUT STD_LOGIC_VECTOR (l DOWNTO 0)
              y     : OUT STD_LOGIC);
END system;
ARCHITECTURE design OF system IS
BEGIN
PROCESS (a, b, c)
VARIABLE z : STD_LOGIC_VECTOR ( l DOWNTO 0);
BEGIN
z(0) := c;
FOR I IN 0 TO l LOOP
x(i) < = a(i) XOR b(i) XOR z(i);
z(i+1) <= (a(i) AND b(i)) OR (a(i) AND z(i)) OR (b(i) AND z(i));
END LOOP;
y <= z(l);
END PROCESS;
END design;

Question 50 of 50


 

Topic wise Test Quizzes on VHDL

VHDL tests, quizzes, and exams are great ways to learn and test your VHDL skills. Whether you’re a beginner or experienced, challenge and boost your confidence with our engaging online quizzes on VHDL Basics, VHDL Data Types, Operators, VHDL Behavioural and Structural Modeling, WAIT Statement, VHDL Function, Predefined Attributes, Reserved Word, VHDL Synthesis, VHDL Combinational Logic Circuit and Design. Start the VHDL online test now!

VHDL Basic Quiz

VHDL Data Types and Operator Quiz

VHDL Behavioural Modeling Quiz

VHDL Structural Modelling Quiz

Sequential Processing Quiz

WAIT Statement Quiz

VHDL Variable Vs Signal Quiz

VHDL Function and Procedure Quiz

VHDL Predefined Attribute Quiz

VHDL Reserved Word Quiz

VHDL Synthesis Quiz

VHDL Combinational Logic Circuit Quiz

VHDL Design Quiz


VHDL Certification Test

VHDL Certification Test is a free certification exam. However, you need to score an A grade in each of the "Certification Level Tests 1 to 10" to be eligible to take part in this certification test. So, take all the "10 Tests" starting from Certification Level 1 upto Level 10, before taking the final Certification test.

Level 1 Test Certification Test

Level 1 to 10 Tests:
Total Questions: 25, Total Time: 30 min, Correct Answer: 2 points, Wrong Answer: -1 point

Certification Test:
Total Questions: 50, Total Time: 1 hour, Correct Answer: 2 points, Wrong Answer: -1 point

VHDL Internship Test

If you scored either Grade A* or Grade A in our VHDL Internship Test, then you can apply for Internship at Sanfoundry in VHDL.

VHDL Internship Test

Total Questions: 50, Total Time: 1 hour, Correct Answer: 2 points, Wrong Answer: -1 point

VHDL Job Test

It is designed to test and improve your skills for a successful career, as well as to apply for jobs.

VHDL Job Test

Total Questions: 50, Total Time: 1 hour, Correct Answer: 2 points, Wrong Answer: -1 point

Note: Before you get started on these series of online tests, you should practice our collection of 1000 MCQs on VHDL .

Sanfoundry Scoring & Grading System

Sanfoundry tests and quizzes are designed to provide a real-time online exam experience. Here is what you need to know about them.

  • Scoring System: You get 2 points for each correct answer but lose 1 point for every wrong answer.
  • Grading System: Your grade depends on your final score and can be one of the following:

    • Grade A* - Genius (100%)
    • Grade A - Excellent (80% to 99%)
    • Grade B - Good (60% to 80%)
    • Grade C - Average (40% to 60%)
    • Grade D - Poor (0% to 40%)
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Manish Bhojasia - Founder & CTO at Sanfoundry
Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He lives in Bangalore, and focuses on development of Linux Kernel, SAN Technologies, Advanced C, Data Structures & Alogrithms. Stay connected with him at LinkedIn.

Subscribe to his free Masterclasses at Youtube & discussions at Telegram SanfoundryClasses.