VHDL Practice Test 1

1. Which of the following is only predefined physical literal in VHDL?

DISTANCE

CURRENT

TIME

VOLTAGE

2. An entity can’t be described by more than one architecture.

False

True

3. In what aspect, HDLs differ from other computer programming languages?

HDLs describe hardware rather than executing a program on a computer

No aspect; both are same

HDLs describe software and not hardware

Other computer programming languages have more complexity

4. How to control the structure and timing of the entity can be changed?

By using TIME variable in the entity

By changing the entity declaration from time to time

By using some special code

By using GENERICS

5. Which of the following is an entity declared for a full adder?

ENTITY full_adder
    PORT(a, b, c : IN BIT;
    s, co : OUT BIT);
   END full_adder;

ENTITY full_adder IS
    PORT (a, b, c, s, co : BIT);
    END full_adder;

ENTITY full_adder IS
    PORT(a, b, c : IN BIT;
    s, co : OUT BIT);
   END full_adder;

ENTITY full_adder IS
    PORT (a ,b : IN BIT;
    s, c : OUT BIT);
    END full_adder;

6. The process of transforming a design entry information of the circuit into a set of logic equations in any EDA tool is known as _________

Synthesis

Simulation

Optimization

Verification

7. SIGNAL a : REAL; which of the following is illegal assignment for a?

a <= 1.0 E-10

a <= 1.0 E10

a <=1.0 ns

a <= 1.8

8. Which of the following can have more than one driver?

OUT

BUFFER

INOUT

9. Driver can be seen as a _______ of the signal.

Source

Type

Final value

Part

10. An entity can have more than one architecture.

False

True