VHDL Mock Test 9 - Sanfoundry

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Question 1 of 10

1. What is the result of flattening of functions?

Increased speed

Decreased readability

Increased readability

Decreased speed

Question 1 of 10

Question 2 of 10

2. In designing logic functions in VHDL, we can use arithmetic operators.

True

False

Question 2 of 10

Question 3 of 10

3. What would be the ideal case for a design?

Using flattening only

Neither using flattening and nor factoring

Using both flattening and factoring

Using factoring only

Question 3 of 10

Question 4 of 10

4. The architecture describes _______ gate implemented by _________ modeling.

ARCHITECTURE my_arch OF my_design IS
BEGIN
y <= NOT(a OR b);
END my_arch;

Not, Dataflow

Or, behavioral

Nor, Dataflow

Nor, behavioral

Question 4 of 10

Question 5 of 10

5. Which of the following represents the correct order?

Implementation, optimized function, given function

Given function, implementation, optimized function

Given function, optimized function, implementation

Optimized function, implementation, given function

Question 5 of 10

Question 6 of 10

6. The odd behavior of gates in dataflow modeling may be the result of ________

Wrong logic definitions

Sequential statements

Concurrency

Inappropriate assignments

Question 6 of 10

Question 7 of 10

7. Which of the following line is correct for detecting positive edge of a clock?

IF (clk’EVENT AND clk = ‘1’)

IF (clk’EVENT OR clk = ‘1’)

IF (clk’EVENT OR clk = ‘0’)

IF (clk’EVENT AND clk = ‘0’)

Question 7 of 10

Question 8 of 10

8. For gates, which of the following modeling style will corresponds to shortest code?

Behavioral

Data flow

Structural

Both data flow and behavioral

Question 8 of 10

Question 9 of 10

9. What is the type of modeling used in the code given below?

ARCHITECTURE my_arch OF my_design IS
BEGIN
y <= ‘1’ WHEN a =’1’ AND b = ‘0’;
       ‘0’ WHEN OTHERS;
END my_arch;

Structural

Behavioral

Dataflow

Combinational

Question 9 of 10

Question 10 of 10

10. A user doesn’t want to use the IF statement for detecting clock edge. It is possible to do the same by using any other keyword in VHDL.

True

False

Question 10 of 10