VHDL Practice Test 2

1. SIGNAL x : STD_LOGIC; In this statement x is ______

2. A buffer with single input A and single output B has a delay of 20 nanosecond. If the value of input A changes after 10 ns from 0 to 1 and it changes again from 1 to 0 at 20 ns. At what time, the value of output B will be 1, if the transport delay model is used?

3. In which part of the VHDL code, generics are declared?

4. Which of the following is the correct syntax for declaring a SUBTYPE?

5. Following waveform shows the output B of a buffer having delay 10 ns for two different delay mechanisms, specify the name of delay mechanism for corresponding waveform.

6. Which of the following is equivalent division by 2 operator?

7. ABS operator is used to _________

8. Which of the following logical operator has the highest precedence?

9. How to correctly assign the value of 2x+10 to y in the following VHDL code?

TYPE long IS INTEGER RANGE -1000 TO 1000;
TYPE short IS INTEGER RANGE -10 TO 10;
SIGNAL x : short;
SIGNAL y : long;

10. Which of the following can’t be the value of x? Refer to the VHDL code given below.

TYPE color IS (red, green, blue, black, white, gray);
SUBTYPE primary IS color RANGE red to blue;
VARIABLE x: primary;