VHDL Practice Test 10

1. How many levels of abstraction are there in the top-level system design?

2. Clock divider slow down the input clock of the shift register.

3. Which of the following is not a combinational circuit?

4. In a given combinational circuit, the concurrent statements are used with selected assignments using WHEN and ELSE keyword. What is the other alternative to implement the same?

5. Asynchronous counters are generally used in circuits with higher frequency, where a large number of bits are involved.

6. Which of the following line of the code contains an error?

L1: ARCHITECTURE mux1 OF mux IS
L2: BEGIN
L3: y<= x0 WHEN x = ‘0’ ELSE
L4:   <= x1 WHEN x = ‘1’;
L5: END mux1;

7. Which of the following tool performs logic optimization?

8. Optimized implementation of Boolean functions reduces the cost of implementation.

9. Setup time is the time required for input data to settle after the triggering edge of the clock.

10. The code given below is a VHDL implementation of _________

ARCHITECTURE my_circuit OF my_logic IS
BEGIN
WITH ab SELECT
y <= x0 WHEN “00”;
         x1 WHEN “01”;
         x2 WHEN “10”;
         x3 WHEN “11”;
END my_circuit;