VHDL Practice Test 4

1. Which of the following is a variable assignment statement?

2. If the condition of IF statement is an expression, then what should be the type of the result of the expression?

Integer

Boolean

Std_logic

Bit

3. A process has a declaration part.

True

False

4. Delays are generally ignored in ________ assignments statements.

Concurrent

Selected

Conditional

Sequential

5. If no signal in the sensitivity list is changed, then how many times the process will be executed?

6. Sensitivity list of a process contains __________

Constants

Variables

Signals

Literals

7. Which of the following is a keyword used for conditional assignment?

END

WHEN

FOR

8. What is the correct syntax for defining an IF statement?

    IF (condition) THEN
    statements;
    ELSIF (condition) THEN
    statements;
    ….;
    ELSE 
    statements;
    END IF-ELSE;

    IF (condition) THEN
    statements;
    ELSIF (condition) THEN
    statements;
    ….;
    ELSE 
    statements;
    END IF;

    IF (condition) THEN
    statements;
    ELSIF (condition) THEN
    statements;
    ….;
    ELSE (condition) THEN
    statements;
    END IF;

    IF (condition) THEN
    statements;
    ELSIF (condition) THEN
    statements;
    ….;
    ELSE (condition)
    statements;
    END IF-ELSE;

9. Which of the following statement is used when there are no signals in the sensitive list?

CASE

WHEN

WAIT

IF ELSE

10. Inertial delay in Signal assignment is useful to ___________

Specify wire delay

Ignore input glitches

No use

Accumulate delay