VHDL Mock Test 10

1. Time taken by the shift register to transfer the content is called _______

2. How many types of shift operators are there in VHDL?

3. Which register is used in the following code?

library ieee;
use ieee.std_logic_1164.all;
entity shift_siso is
port (Clock, Sin : in std_logic;
Sout : out std_logic);
end shift_siso;
architecture behav of shift_siso is
signal temp: std_logic_vector(7 downto 0);
begin
process (Clock)
begin
if (Clock'event and Clock='1') then
for i in 0 to 6 loop
temp(i+1) <= temp(i);
end loop;
temp(0) <= Sin;
end if ;
end process;
Sout <= temp(7);
end behav;

4. Shift registers comprise of which flip-flops?

5. A 4 to 16 decoder can be used as a code converter. What will be the inputs and outputs of the converter respectively?

6. What will be the value of count output, if the data din is 11001111?

ENTITY my_logic IS
PORT (din : STD_LOGIC_VECTOR(7 DOWNTO 0);
             Count : STD_LOGIC_VECTOR(3 DOWNTO 0));
END my_logic;
ARCHITECTURE behavior OF my_logic IS
BEGIN
Count <= “0000”
PROCESS(din)
BEGIN
L1: FOR i IN 0 TO 7 LOOP
IF(din(i) = ‘1’) THEN
Count = count+1;
ELSE
NEXT L1;
END LOOP;
END PROCESS;
END behavior;

7. State transition happens _______ in every clock cycle.

8. In the FSM diagram, what does arrow between the circles represent?

9. Which of the following react faster to inputs?

10. What is the first step in writing the VHDL for an FSM?