VHDL Mock Test 2

1. One can perform basic operations between different data types.

2. Look at the following declarations:

TYPE array1 IS ARRAY ( 0 TO 3 ) OF BIT_VECTOR (3 DOWNTO 0 ); 
TYPE array 2 IS ARRAY ( 0 TO 3 ) OF array1;

How many total bits can be stored in these arrays?

3. Which of the following package of IEEE contains most of the data conversion functions?

4. One can’t define an array without any constraints in VHDL.

5. A VARIABLE y is declared of STD_LOGIC_VECTOR type of 4 bits, if you want to assign 1001 to y, then what is the write assignment statement?

6. Which of the circuit is described by following VHDL code?

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY my_func IS
PORT(x, a, b : IN std_logic;
q : OUT std_logic);
END my_func;
ARCHITECTURE behavior OF my_func IS
SIGNAL s : INTEGER;
BEGIN
WITH s SELECT
q <= a AFTER 10 ns WHEN 0;
         b AFTER 10 ns WHEN 1;
s <= 0 WHEN x = ‘0’ ELSE
        1 WHEN x = ‘1’;
END behavior;

7. Which of the following is not an assignment operator?

8. What is the use of simulation deltas in VHDL code?

9. How to correctly assign the value of 2x+10 to y in the following VHDL code?

TYPE long IS INTEGER RANGE -1000 TO 1000;
TYPE short IS INTEGER RANGE -10 TO 10;
SIGNAL x : short;
SIGNAL y : long;

10. If we are using conv_integer(p) function, then which of the following cannot be the type of parameter ‘p’?