Digital Circuits Practice Test 6

1. The flip-flops which has not any invalid states are _____________

2. A positive edge-triggered D flip-flop will store a 1 when ________

3. When a high is applied to the Set line of an SR latch, then ___________

4. Which circuit is generated from D flip-flop due to addition of an inverter by causing reduction in the number of inputs?

5. The characteristic equation of J-K flip-flop is ______________

6. Master slave flip flop is also referred to as?

7. The full form of SR is ___________

8. The D flip-flop has _______ input.

9. Which of the following is the Universal Flip-flop?

10. For realisation of JK flip-flop from SR flip-flop, the input J and K will be given as ___________