Digital Circuits Mock Test 6

10%

Question 1 of 10

1. What is one disadvantage of an S-R flip-flop?

Invalid State

It has no clock input

It has no Enable input

It has a RACE condition

Question 1 of 10

Question 2 of 10

2. For realisation of JK flip-flop from SR flip-flop, if J=0 & K=0 then the input is ___________

S=X, R=0

S=0, R=0

S=X, R=X

S=0, R=X

Question 2 of 10

Question 3 of 10

3. The asynchronous input can be used to set the flip-flop to the ____________

1 state

0 state

either 1 or 0 state

forbidden State

Question 3 of 10

Question 4 of 10

4. D flip-flop is a circuit having ____________

4 NAND gates

5 NAND gates

2 NAND gates

3 NAND gates

Question 4 of 10

Question 5 of 10

5. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________

The clock pulse is HIGH

The clock pulse is LOW

The clock pulse transitions from LOW to HIGH

The clock pulse transitions from HIGH to LOW

Question 5 of 10

Question 6 of 10

6. The term synchronous means ____________

The output changes state only when the input is reversed

The output changes state only when the input follows it

The output changes state only when any of the input is triggered

The output changes state only when the clock input is triggered

Question 6 of 10

Question 7 of 10

7. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?

Low input voltages

Synchronous operation

Cross coupling

Gate impedance

Question 7 of 10

Question 8 of 10

8. The first step of the analysis procedure of SR latch is to ___________

label inputs

label states

label outputs

label tables

Question 8 of 10

Question 9 of 10

9. The circuit that generates a spike in response to a momentary change of input signal is called ____________

L-R integrator circuit

L-R differentiator circuit

R-C differentiator circuit

R-C integrator circuit

Question 9 of 10

Question 10 of 10

10. The output of latches will remain in set/reset untill ___________

They don't get any pulse more

The pulse is edge-triggered

Any pulse given to go into previous state

The trigger pulse is given to change the state

Question 10 of 10