Microcontroller Practice Test 5

1. Is the same address is assigned for the timer0 and timer1 overflow flag in the interrupt vector table of the interrupts?

true

depends on the situation

false

can't be determined

2. The USART in AVR based microcontrollers operate at which of the following modes?

slave synchronous

double speed asynchronous mode

master synchronous

all of the mentioned

3. What is the use of the PE and the FE bits of the UCSRA register?

they are used to keep the transmission error free

they are used as extra redundant bits with no use

they are used for keeping a check at the speed of transmission and reception

they are used for keeping a check at the data bits to be transferred

4. Identify the row and the column for the following case when for the row D3-D0= 1110 and for the column D3-D0= 1101

second row and second column

first row and second column

second row and first column

first row and third column

5. On reset, what are the contents of the SREG register?

1fh

11h

00h

ffh

6. Which resource provides the clock pulse to AVR timers if CS02-00=6?

all of the mentioned

external clock of the AVR

internal clock of the AVR

none of the mentioned

7. Which register is responsible for handling all the external hardware interrupts?

IVCE

MCUCR

TIMSK

GICR

8. Which of the following is correct about the word resolution in ADC DAC converters in AVR's?

all of the mentioned

it is equal to Vref/2ⁿ (where n represents the number of bits)

it is the smallest change that can be described by an ADC

it is 0.076mV or 76uV for n=16 and Vref=5V

9. Why RETI instruction be the last instruction of ISR?

because it returns with carry

because it returns to the main program with all the flags of the SREG raised

because it returns to the main program where interrupt is generated and set the global interrupt enable bit in SREG

none of the mentioned

10. If the pins of the keyboard are used as an interrupt, then these pins will cause an interrupt of what type?

Timer interrupt

External hardware interrupt

TI/RI interrupt

None of the mentioned