Microprocessor Online Test

1. The mode that is programmed using "end interrupt/error mode set command" is

2. In general, the destination operand of an instruction can be

3. The HDD is also called as

4. The descriptors that are used for subroutines and interrupt service routines are

5. The data bus buffer is controlled by

6. The operation that is provided by the internal architecture, to save the execution state of a task is

7. For enhancement of processor performance, beyond one instruction per cycle, the computer architects employ the technique of

8. In protected mode of 80386, the VM flag is set by using

9. The unit that may acts as an interface between the Front end and the Out of order execution engine in the pipeline flow is

10. The instruction that is not operated on quad word is

11. Which of the following is true while executing data transfer instructions?

12. The instruction that multiplies the content of AL with a signed immediate operand is

13. The mechanism that is accomplished using descriptor usages limitations and rules of privilege check is

14. Which of the following is an incorporated function to resolve interprocessor communication problems?

15. The signal that is used to drive a priority resolving network that actually accepts the bus request inputs is

16. The field in which dynamic RAM is more complicated than static RAM is

17. Which of the following group is not of SSE instructions?

18. The gate that is used to specify a corresponding service routine is

19. While retrieving data from the stack, the stack pointer is

20. The directive that marks the end of a logical segment is

21. Which of the following is an 8-bit register?

22. An interrupt breaks the execution of instructions and diverts its execution to

23. The selector RPL that uses a less trusted privilege than the current privilege level for further use is known as

24. The architecture of CPU of Pentium III is suitable for

25. The instruction that adds immediate data/contents of the memory location specified in an instruction/register to the contents of another register/memory location is

26. The maximum current that can be sinked totally by all the ports of 8051 is

27. The new instructions that are added in SSE for floating point operations are of

28. The stage in which the CPU generates an address for data memory references in this stage is

29. The instruction that loads the AH register with the lower byte of the flag register is

30. Distributed systems are designed to run

31. The memory management unit consists of

32. The processors used in the multi-microprocessor are

33. The memory management of 80386 supports

34. In case of BT instruction, if the bit position in the destination operand specified by the source operand, is '1', then

35. The mcs 51 architecture supports

36. The device that is used for deriving chip select signals is

37. With the trailing edge of the LOCK (active low), the INTA (active low) goes low and remains in it for

38. If 'n' denotes the number of clock cycles and 'T' denotes period of the clock at which the microprocessor is running, then the duration of execution of loop once can be denoted by

39. The signal, SLCT in the direction of signal flow, OUT, indicates the selection of

40. If the segment descriptor bit, S=0, then the descriptor is

41. The clock frequency applied at the CLK pin is internally divided by

42. The statement that is true for the instruction POP*A is

43. The number of interrupt descriptors that the interrupt descriptor table (IDT) handles is

44. The number of instructions that can be executed per clock cycle by the ALU or AGU is

45. The flag that is additional in flag register of 80386, compared to that of 80286 is

46. Which of the following is not an addressing mode of 8051?

47. During the execution of instructions, if an instruction is executed, then next instruction is executed only when the data is read by

48. The pin that strobes the higher byte of the memory address, generated by the DMA controller into the latches is

49. In 8257 register format, the selected channel is disabled after the terminal count condition is reached when

50. Which of the following is not one of the phases of the total conversion cycle?