VHDL Design Test – 2

1. Two decade counters cascaded together will divide the input frequency by ________

2. Synchronous counter use ________ global clock, unlike asynchronous counter.

3. ‘shift_reg’ is used to initialize the _____________ in the shift register.

4. The number of flip-flops used in a counter is _________ number of states in the counter.

5. Which of the following flip-flop is used by the ring counter?

6. In __________ counter universal clock is not used.

7. Asynchronous counters are generally used in circuits with higher frequency, where a large number of bits are involved.

8. How many different states does a decade counter count?

9. The ring counter is a serial shift register with feedback from the output of the last flip-flop to the input of the first flip-flop.

10. How many types of the data type are there in the ring counter?

11. How many types of shift operators are there in VHDL?