Logic Gate Test - Sanfoundry

1. The following switching functions are to be implemented using a decoder:
f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will be __________

4 to 16 line

3 to 8 line

5 to 32 line

2 to 4 line

2. The code where all successive numbers differ from their preceding number by single bit is __________

Excess 3

Gray

Alphanumeric Code

BCD

3. Which of the following are known as universal gates?

NAND & NOR

XOR & OR

AND & OR

EX-NOR & XOR

4. How many AND gates are required to realize Y = CD + EF + G?

5. The NOR gate output will be high if the two inputs are __________

6. How many two input AND gates and two input OR gates are required to realize Y = BD + CE + AB?

2, 3

1, 1

4, 2

3, 2

7. The output of a logic gate is 1 when all the input are at logic 0 as shown below:

INPUT		OUTPUT
A	B	C
0	0	1
0	1	0
1	0	0
1	1	0

INPUT		OUTPUT
A	B	C
0	0	1
0	1	0
1	0	0
1	1	1

The gate is either _________

A NAND or an EX-OR

A NOR or an EX-NOR

An AND or an EX-OR

An OR or an EX-NOR

8. A full adder logic circuit will have __________

Two inputs and one output

Three inputs and two outputs

Two inputs and two outputs

Three inputs and three outputs

9. How many two-input AND and OR gates are required to realize Y = CD+EF+G?

3, 2

2, 2

2, 3

3, 3

10. The gates required to build a half adder are __________

EX-NOR gate and AND gate

EX-OR gate and OR gate

EX-OR gate and AND gate

EX-OR gate and NOR gate