Flip Flop Test - Sanfoundry

1. What is an ambiguous condition in a NAND based S'-R' latch?

S'=0, R'=0

S'=1, R'=0

S'=0, R'=1

S'=1, R'=1

2. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________

RESET

Clear

Invalid

SET

3. One major difference between a NAND based S'-R' latch & a NOR based S-R latch is ____________

The inputs of NOR latch are 0 but 1 for NAND latch

The output of NOR latch is 1 but 0 for NAND latch

The output of NAND latch becomes set if S'=0 & R'=1 and vice versa for NOR latch

The inputs of NOR latch are 1 but 0 for NAND latch

4. The characteristic equation of S-R latch is ____________

Q(n+1) = (S + Q(n))R'

Q(n+1) = SR + Q(n)R

Q(n+1) = S'R + Q(n)R

Q(n+1) = S'R + Q'(n)R

5. The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the _____________

Edge-detection circuit

NAND latch

Pulse-steering circuit

NOR latch

6. A NAND based S'-R' latch can be converted into S-R latch by placing ____________

It can never be converted

Both a D latch and an inverter at its input

An inverter at each of its input

A D latch at each of its input

7. The difference between a flip-flop & latch is ____________

Flip-flop consist of an extra output

Latch has two inputs but flip-flop has one

Both are same

Latches has one input but flip-flop has two

8. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________

The clock pulse is HIGH

The clock pulse transitions from HIGH to LOW

The clock pulse is LOW

The clock pulse transitions from LOW to HIGH

9. What is the hold condition of a flip-flop?

Only S is active

Only R is active

Both S and R inputs activated

No active S or R input

10. The S-R flip flop consist of ____________

Two additional AND gates

4 AND gates

An additional clock input

3 AND gates

11. One example of the use of an S-R flip-flop is as ____________

Binary storage register

Transition pulse generator

Stable oscillator

Racer

12. When is a flip-flop said to be transparent?

When the Q output is complementary of the input

When you can see through the IC packaging

When the Q output is opposite the input

When the Q output follows the input

13. In a NAND based S'-R' latch, if S'=1 & R'=1 then the state of the latch is ____________

Forbidden

Reset

Set

No change

14. How many types of flip-flops are?

15. What is one disadvantage of an S-R flip-flop?

It has no clock input

It has a RACE condition

Invalid State

It has no Enable input