Digital Register Test – 2

1. A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?

2. An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time delay between the serial input and the Q3 output?

3. A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by ________ position for each clock pulse.

4. What are the three output conditions of a three-state buffer?

5. How many clock pulses will be required to completely load serially a 5-bit shift register?

6. To operate correctly, starting a ring shift counter requires __________

7. How is a strobe signal used when serially loading a shift register?

8. The primary purpose of a three-state buffer is usually ____________

9. A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing ________

10. What is the difference between a ring shift counter and a Johnson shift counter?