Digital Integrated Circuit Test

1. Logic circuits that are designated as buffers, drivers or buffers/drivers are designed to have _______________

A smaller output current/voltage capability than an ordinary logic

Greater the input and output current/voltage capability than an ordinary logic circuit

A greater current/voltage capability than an ordinary logic circuit

Greater input current/voltage capability than an ordinary logic circuit

2. Which of the following statements apply to CMOS devices?

The devices should not be inserted into circuits with the power on

All of the Mentioned

All tools, test equipment and metal workbenches should be tied to earth ground

The devices should be stored and shipped in antistatic tubes or conductive foam

3. Which of the following will not normally be found on a data sheet?

Maximum HIGH level input current

Minimum LOW level output voltage

Maximum LOW level output voltage

Minimum HIGH level output voltage

4. What must be done to interface TTL to CMOS?

As long as the CMOS supply voltage is 5 V they can be interfaced (however, the fan-out of the TTL is limited to five CMOS gates)

A pull-up resistor must be used between the TTL output-CMOS input node and Vcc; the value of RP will depend on the number of CMOS gates connected to the node

A 5 V zener diode must be placed across the inputs of the TTL gates in order to protect them from the higher output voltages of the CMOS gates

A dropping resistor must be used on the CMOS of 12 V supply to reduce it to 5 V for the TTL

5. What causes low-power Schottky TTL to use less power than the 74XX series TTL?

A small value resistor

The Schottky-clamped MOSFET

A larger value resistor

The Schottky-clamped transistor

6. Which of the following logic families has the highest maximum clock frequency?

HS-TTL

HCMOS

S-TTL

AS-TTL

7. What is the static charge that can be stored by your body as you walk across a carpet?

Over 30000 volts

300 volts

3000 volts

30000 volts

8. Why is the fan-out of CMOS gates frequency dependent?

The input gates of the FETs are predominantly capacitive and as the signal frequency increases the capacitive loading also increases thereby limiting the number of loads that may be attached to the output of the driving gate

When the frequency reaches the critical value the gate will only be capable of delivering 70% of the normal output voltage and consequently the output power will be one-half of normal and this defines the upper operating frequency

Each CMOS input gate has a specific propagation time and this limits the number of different gates that can be connected to the output of a CMOS gate

The higher number of gates attached to the output the more frequently they will have to be serviced thus reducing the frequency at which each will be serviced with an input signal

9. What are the major differences between the 5400 and 7400 series of ICs?

The 7400 series was originally developed by Texas Instruments and the 5400 series was brought out by National Semiconductors after TI's patents expired as a second supply source

The 5400 series are military grade and allow for a wider range of supply voltages and temperatures

The 7400 series are an improvement over the original 5400s

The 5400 series are military grade and require tighter supply voltages and temperatures

10. Which of the following logic families has the shortest propagation delay?

S-TTL

HS-TTL

HCMOS

AS-TTL